||Verifier is an industry leading comprehensive solution to the problem of creating
First pass ATE test programs from the design generated simulation/ATPG test vectors. Verifier seamlessly integrates into the design flow improving communication between the design and test and reducing post-silicon debug time.
||Simutest announces the ATE-Ready. The ATE-Ready is a pattern conversion and verification software that accepts functional test vectors in the VCD/EVCD or tabular format as inputs and generates cyclized test vectors in the industry standard test vector formats such as WGL or STIL. The ATE-Ready software has built-in capability to analyze the input test vectors against the tester capabilities and restrictions to ensure that the generated WGL or STIL files are compatible with the target ATE. In addition, the ATE-Ready software also provides capability to playback the cyclized vectors in the Verilog simulation to validate that the generated WGL or STIL files meet the design intent.
||The SiliconDebug is a software product that maps the ATE captured data log of silicon failures into the design environment. For graphical viewing of silicon failures, the ATE-debug software generates a VCD file. User has flexibility to select the signals and time intervals for display. E.g. the VCD file may contain waveforms for all device pins or waveforms for only the failing pins or waveforms for the selected pins during the fail time interval(s). Additionally, the compare module of the SiliconDebug software compares and reports the differences between the source simulation patterns with silicon captured patterns or ATE stored patterns in a text report file.
||The Scan Converter is low cost and versatile test pattern translation software. The Scan Converter efficiently converts STIL or WGL files, generated by EDA tools into the test programs for more than for more than 70 models from most major ATE systems including those from Advantest, Verigy, Teradyne, and Credence.
||Rule Analyzer is a test vector analysis product that can be used to analyze simulation or ATPG generated test vectors against a set of user defined rules. The Rule Analyzer product can be used in either design or test environment to identify compatibility of design test vectors against a particular test methodology or target ATE capabilities and restrictions.
|Test Program Builder
||The TP-Builder is a custom software framework for automating the process of development of complete test programs for the production test systems for a set of structured digital devices. The TP-builder framework integrates the vector conversion with the parametric DC tests thus creating standardized production test programs in a matter of minutes instead of days.
|Tester to Tester
||T2T is a conversion program that converts existing test program (vectors, timings and pin definition) from one tester to another. T2T can output directly into the native test language of the target ATE or can output in ATE acceptable or IEEE standard STIL format.
||Simcompare is a comparison program that compares test vectors between: 1) Best Vs. worst case simulations; 2) Simulation test vectors Vs. ATE vectors; or 3) Source ATE vectors Vs. target ATE vectors.
||Solution for keeping track of changes to your test programs and data by incorporating version control, defect tracking, and release management.