|The Verifier Difference
Verifier features an easy-to-use graphical user interface which reduces the test program development time. To save time and reduce costly iterations between design and test, Verifier has a powerful tester rule checker that reveals potential tester compatibility issues early in the test pattern generation process. A multi-channel waveform display together with extensive timing analysis reports produced by Verifier makes it easy to spot and remove simulation artifacts. Verifier provides advanced features such as automatic timing and time sets extraction, the ability to handle multiple simulation files with incremental timings for optimization as well as support for pattern compression for repeats, subroutines and loops extracted directly from simulation or ATPG vectors. In addition Verifier can also produce equation-based timings in tester format that helps test engineers quickly characterize the device.